New

PrincipalAI NetworkHWSystems Engineer

Microsoft
$142,800.00 - $274,800.00 / yr
United States, Washington, Redmond
Jul 14, 2026
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers the infrastructure behind Microsoft's Intelligent Cloud, delivering the foundational technologies that support services including Azure, Microsoft 365, Teams, Bing, Xbox Live, and more. As Microsoft continues to advance AI innovation, SCHIE is developing AI-native silicon and system-level solutions that enable next-generation AI training and inference at hyperscale. The Platform Systems Engineering (PSE) team is seeking a Principal AI Network Hardware Systems Engineer to lead the architecture, bring-up, validation, optimization, and deployment of networking infrastructure for Microsoft's MAIA AI platform. This role combines networking hardware, systems architecture, AI infrastructure, and large-scale deployment to deliver industry-leading AI performance and reliability. You will work across the networking stack, spanning high-speed SerDes, optics, cables, NICs, PHYs, switch silicon, AI communication frameworks, and distributed training systems. As a Principal engineer, you will influence architectural direction, guide technical strategy, and collaborate across silicon, firmware, hardware, software, validation, manufacturing, and Azure engineering teams. This is a unique opportunity to shape the future of AI networking infrastructure and drive technologies that power Microsoft's next generation of hyperscale AI systems. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Responsibilities Own AI networking architecture for MAIA training and inference systems across scale-up and scale-out deployments. Lead integration and qualification of switches, NICs, PHYs, optics, cables, and high-speed SerDes technologies. Define validation strategies covering functionality, interoperability, performance, scale, reliability, and stress testing. Optimize AI fabric performance through analysis of latency, bandwidth utilization, congestion management, and collective communication efficiency. Drive debugging, telemetry, and automation solutions that improve network resiliency and operational excellence. Evaluate next-generation networking technologies and influence Microsoft's future AI infrastructure roadmap. Qualifications Required Qualifications: Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR equivalent experience 8+ years of experience in NW HW development 8+ years of experience in GPU based SU/SO development 8+ years of hands on experience with HS interface architecture and development Other Qualifications: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Preferred Qualifications: AI Infrastructure Experience Experience developing GPU, FPGA, TPU, AI accelerator, or HPC-based systems. Familiarity with AI workload communication patterns and collective operations. Understanding of large-scale distributed AI training environments. Optical & Interconnect Expertise Deep knowledge of: Optical transceivers (DR4, DR8, FR4) DSParchitectures TIAs and drivers Optical link budgets OMA, TDECQ, receiver sensitivity analysis Silicon photonics technologies Co-packaged opticsarchitectures Industry Standards Experience with: IEEE Ethernet standards OIF specifications CMIS management frameworks Ultra Ethernet Consortium technologies Future 224G and 448G ecosystems Datacenter & Manufacturing Experience with hyperscale datacenter deployments. Knowledge of ODM, CM, and supplier ecosystems. Experience managing products through EVT, DVT, PVT, and production ramps. Software & Automation Experience with Linux environments and automation frameworks. Background developing telemetry, diagnostics, validation, and qualification tooling. Familiarity with scripting and data analysis environments. #azure#MAIA#AI/ML#Networking Hardware Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.