Job Title: ASIC Power Engineer
Location: Sunnyvale CA - Hybrid
Duration: 6 months, potential extension
Job Description:
Role: ASIC Power Engineer
Duties:
ASIC Power Engineer to perform power analysis and optimizations in ASIC for Client's AR/VR products. Areas of interest include Machine Learning. Primary languages are Python, Tcl, and SystemVerilog.
Must-Have Skills
- Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
- Should know how to use Python, Perl (or similar) scripting and data post-processing tools.
- Experience in low-power design, tools, and methodologies, including power intent UPF specifications.
Silicon power characterization.
Nice-to-have Skills
- Some power profiling experience at IP/SoC level.
- Experience with silicon power characterization.
- Experience with data analytics and visualization
Years of Experience:
- 10+ years of experience as an ASIC Power Engineer or CAD Engineer/Physical Design Engineer.
Responsibilities:
- Perform PPA optimization with Fusion Compiler.
- Perform RTL and netlist-level power analysis.
- Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
- Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
- Implement some blocks at RTL and UPF.
- Ability to document and communicate clearly.
Minimum Qualifications:
- 10+ years of experience as an ASIC Power Engineer or CAD Engineer/Physical Design Engineer.
- Experience with power estimation tools and synthesis, some physical design.
- Knowledge of power trade-offs in design and backend implementation.
- Hands-on experience in scripting and data analysis.
- BS in Electrical Engineering/Computer Science or equivalent experience.
Preferred Qualifications:
- Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
- Python, Perl (or similar) scripting and data post-processing tools.
- Excel (or Matlab) for model fitting, data visualization, and analysis.
- Experience in low-power design, tools, and methodologies, including power intent UPF specifications.
- Silicon power characterization.
- Some power profiling experience at IP/SoC level.
Key Projects/Day-to-Day Responsibilities:
- Perform PPA optimization with Fusion Compiler.
- Perform RTL and netlist-level power analysis.
- Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
- Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
- Implement some blocks at RTL and UPF.
- Ability to document and communicate clearly.
How will performance be measured?
- Based on rubrics, who handle 80% of their responsibilities.
What makes this role interesting?
- Designing the most advanced chips for AR/VR devices. Client owns the major market for VR devices. There are many opportunities to learn how to build chips for AR/VR products.
Value added or experience gained:
- CW will learn how to build a chip and also how to collaborate with software and hardware folks.
Degrees/Certifications Required:
- BS in Electrical Engineering/Computer Science or equivalent experience.
How many rounds of interviews? 2
Types of Interviews: Technical
Interview Duration: 30 minutes
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Spectraforce Technologies
Apr 02, 2026