Staff Engineer, Design Verification

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

Develop verification of Marvell's AI/ML, Network processing, Compute, Automotive, and Baseband SoCs and IPs. Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology. Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete. Develop tests and tune the environment to achieve coverage goals. Debug failures and work with designers to resolve issues. Architect, develop, and maintain tools to streamline the design of state-of-the-art multicore SoCs. Wage: $162,000.00 - $182,000.00 per year.

What We're Looking For

Master's or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and two (2) years of experience in the job offered or related occupation.

Experience must include two (2) years with each of the following:
* Analysis/closure of code and functional coverage.
* Developing complex/random verification environments using System Verilog/UVM.
* Writing and executing detailed verification test-plan.
* Semiconductor Design Verification techniques including assertions, constraints, coverage, modeling and interfaces.
* Scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms.
* Object-oriented programming languages including C, C++.
* Working on verification environments for subsystems that contain networking components, and bus protocols like AHB.
* Protocols such as PCIe and Ethernet.
* Post-Silicon validation and debug.
* Gate Level Simulations.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.