Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Physical Design Engineer to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AISiE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Physical Design Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Physical Design Engineer to join the team.

We are seeking a Principal Physical Design Engineer to join our dynamic team. As a Principal Physical Design Engineer, you willbe responsible fordelivering TFM (tool, flow and methodology) of Physical Design tasks at block, sub-chip, and/or full-chip level. The tasks include one of the following -Place and Route (PnR), Static Timing Analysis (STA), Physical Verification (PV), Formal Equivalency Verification (FEV), Functional ECO, Clocking Construction and IR-Drop/EM (EMIR) with details below:

• Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level.
• Develop and implement methodologies and strategies to improve physical design efficiency and performance.
• Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop.
• Implementation of functional ECO with least physical design impact.
• Design and implement the global clocking scheme at SOC and sub chip levels.
• Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies.
• Installation and quality check of internal and external IP collaterals for use by Physical Design execution team.
• Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers.

Required Qualifications:

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.As a condition of employment, the successful candidate will be requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status(e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

• Bachelor's or Master's in Electrical or Computer Engineering or related field with 10+ years of experience.
• Experience in tapeouts of complex ASICs in leading edge technology.
• 10+ years of experience in blocks level place and route.
• Expertise in one or more of physical design EDA tools such as Synopsys Fusion Compiler, Primetime, Formality, VCLP, Star-RC and Cadence Innovus; Siemens Calibre.
• Good understanding of semiconductor design principles, methodologies, and tools.
• Proven track record of successfully leading physical design projects and delivering high-quality semiconductor products.
• Adequate scripting skillsets in TCL and Python.
• Effective communication, teamwork, and leadership skills.
• Ability to work in a fast-paced and dynamic environment, and drive cross-functional collaboration.
• Good understanding of foundry tech files and rule decks

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