New 
Senior Design Verification Engineer
 Microsoft | |
 United States, Washington, Redmond | |
 Sep 05, 2025 | |
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OverviewMicrosoft Azure is building the fastest network in public cloud transforming industries into an advanced technological age utilizing high-speed cloud computing, artificial intelligence (AI) and machine learning (ML). In Azure Core our focus is on building Azure capabilities to impact industries ranging from energy and agriculture to healthcare and personal banking. Azure has made Microsoft one of the biggest players in the public cloud domain, where there is tremendous potential to revolutionize the industry through data driven innovation and ecosystems to advance achievements in technology, shaping the future of for million across the world.As a Design Verification Engineer working in Azure Core, you will verify complex designs, define and execute on verification plans, develop System Verilog testbenches using Universal Verification Methodology (UVM). Additionally you will closely collaborate with firmware, software, and hardware development teams spanning sites and geographies to ensure the production of high-quality designs for Fully Programable Gate Arrays (FPGAs) for millions of servers for the cloud. This opportunity will allow you to build technical leadership skills, develop or enhance your skill using UVM for verification learning advanced techniques for unique applications. As a small verification team, your contributions in design verification are high impact with high visibility while having opportunities to learn and growth in any areas which align with your career development goals. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities* You will write design verification test cases by identifying new tools, test methodologies, and/or best practices that include elements such as success metrics and tracking systems and develop, review and execute test plans for complex or large sized scope feature areas or products and execute test plans.* Generate or contribute to a single or multiple project implementation schedules and determine how changes to project schedules and proposed designs impact hardware verification.* You will generate a single project implementation schedule, monitors performance against schedules, and helps determine dependencies and requirements for hardware design verification of complex features for Azure products. Guide, monitor, and track performance of team members contributing towards verification as a technical lead..* Advise others regarding the appropriate test requirements and improvements to be included in relevant, highly complex hardware designs and specifications and review documentation to help ensure that the appropriate test requirements and improvements are included in relevant hardware designs and specifications by applying an understanding of how complex features or products work under a variety of scenarios.* Develop System Verilog based testbenches using Universal Verification Methodology (UVM) testbenches for use within block level and subsystem level test environments along with reusable, configurable verification components for use across verification teams and to be leveraged for future design verification applications and projects | |