Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

An RTL Design Verification Engineering role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your multi-years expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

THE PERSON:

A talented hardware/firmware co-design/verification engineer with strong records of multi-years technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

KEY RESPONSIBILITIES:

• Develop and maintain block level IP and/or MP subsystem verification architecture, testbenches, test methodology and infrastructure
• Acquire hardware IP spec understanding and develop/debug test plans using System Verilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
• Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
• Participate in subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
• Debug and solve integration issues with SoC Integration and SoC DV teams
• Provide technical leadership in verification methodology development and critical problem resolution
• Provide project execution leadership with a span of 5 - 10 team members in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting

PREFERRED EXPERIENCE :

• Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge on applicable state-of-art verification methodology and best practices.
• Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
• Proven skills in creating UVC and other UVM components. Experience with C-DPI and FPV techniques are valuable assets.
• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.
• Relevant design domain specific knowledge and technical leadership capability.

ACADEMIC CREDENTIALS:

• Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
• Master's Degree preferred.

LOCATION: Austin, TX

#LI-SL3

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.