Senior Staff Product Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Own new product introduction (NPI) activities including test characterization, yield ramp, and manufacturability.
• Partner with design, DFT/DFM, process, and test teams to optimize product performance and cost.
• Analyze volume production data to diagnose and resolve test coverage, yield, or quality issues using ATE and lab bench debug techniques.
• Lead yield improvement and cost reduction efforts across multiple test insertions (Wafer Sort, Final Test, SLT).
• Define production test specs, screening limits, and flow optimizations that balance DPPM, quality, and cycle time.
• Drive customer return (RMA) analysis, root cause investigations, and corrective actions alongside quality and customer teams.
• Support qualification efforts for new silicon, packages, and manufacturing sites.

What We're Looking For

• Bachelor's degree in Electrical/Electronic Engineering or a related field; Master's preferred or equivalent practical experience.
• 7+ years of experience in semiconductor product engineering, preferably in high-speed digital or mixed-signal ICs.

Preferred Skills

• Experience in AI infrastructure or cloud datacenter products.
• Exposure to high-speed SerDes, DSP, or coherent optical transceivers.
• Proficiency in Python, JMP, or similar data analytics tools.
• Prior work with RMA and customer-facing issue resolution.
• Hands-on experience with ATE platforms (e.g., Advantest 93K, Teradyne), test program debug, and test data analysis.
• Strong understanding of semiconductor manufacturing, yield analysis tools, and statistical process control (GR&R, Cp/Cpk).
• Demonstrated success in debugging analog/digital circuit behavior, root cause analysis, and implementing corrective actions.
• Familiarity with DFT/DFM techniques and silicon bring-up methodology.
• Experience supporting volume manufacturing ramp and test release at global foundries or OSATs.
• Ability to lead cross-functional initiatives, work independently, and manage complex problem-solving.

Work Location & Schedule

• This is a full-time, on-site position based in Santa Clara, CA. Due to the highly collaborative and hands-on nature of this role, remote or hybrid work is not available

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.