Senior Principal Design Verification Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Mar 07, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Solutions develops cutting-edge solutions for large AI, cloud data center, and telecom customers. The SoCs encompass best-in-class performance, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design Verification Team, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use highly advanced technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major hyperscaler company or telecom organization, etc. What You Can Expect Architect and implement simulation test bench in UVM. Develop and execute test-plans for verifying correctness and performance of the design. Own and debug failures in simulation to root-cause problems Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes. What We're Looking For Bachelor's degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. OR Master's degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. OR PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience. Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI. Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure). Must have effective interpersonal and teamwork skills. Participate in problem solving and quality improvement activities. Demonstrate initiative and a bias for thoughtful action. Grounded, detail-oriented, always backs up ideas with facts. Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets. Expected Base Pay Range (USD) 168,920 - 253,000, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-TM1