Physical Design Principal Engineer

Our client is seeking a highly skilled and experienced Physical Design Principal Engineer to join their dynamic team. In this critical role, you will oversee the entire System-on-Chip (SoC) implementation and verification process, from RTL-to-GDS. Your responsibilities will include floor planning, place and route, clock tree synthesis (CTS), static timing analysis (STA), and physical verification (PV/EMIR/Noise/SigEM) cleanup and signoff. You will contribute to cutting-edge projects within a leading fabless wireless semiconductor platform company, specializing in ultra-low-power wireless radio solutions.

Key Responsibilities:

• Execute complete physical implementation at block and chip levels.
• Perform synthesis and physical implementation tasks, including floor-planning, power delivery, place & route, timing noise analysis, physical verification, and IR/RV analysis.
• Collaborate with the SoC design team to conduct architectural feasibility studies and establish design targets for timing, power, and area.
• Analyze floorplan quality, customized clock tree structures, and place & route efficiency.
• Implement ECOs for timing closure and resolve Signal EM/Noise and Power IR/EM issues.
• Conduct DRC/LVS/ERC/ANTENNA analysis and ensure thorough cleanup.
• Lead timing verification and signoff, along with final physical verification and signoff.

• Master's degree in Electrical/Computer Science Engineering with 12+ years of industry experience, or a Bachelor's degree with 18+ years of industry experience.
• Proven expertise in Netlist (or RTL)-to-GDS physical implementation.
• Comprehensive knowledge of major EDA tools and design flows.
• Hands-on experience with TSMC N22 or below technology nodes.
• Extensive experience in chip integration and signoff processes.
• Proficiency in programming with Perl and TCL.

• Deep understanding of low-power implementation methodologies.
• Advanced knowledge of timing signoff methodologies.
• Familiarity with Design-for-Test (DFT) concepts such as BSCAN, MBIST, and SCAN, and their impact on physical design flows.
• Demonstrated ability to independently execute Netlist-GDS place & route and signoff tasks.
• Successful track record in managing multi-million gate design production tapeouts.